- 封装:16-SSOP(0.209",5.30mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.231-$0.65
更新日期:2024-04-01 00:04:00
产品简介:双路可重触发单稳多频振荡器
查看详情- 封装:16-SSOP(0.209",5.30mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.231-$0.65
SN74LV123ADBR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
SN74LV123ADBR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 多频振荡器
- 系列:74LV
- 逻辑类型:单稳态
- 独立电路:2
- 施密特触发器输入:是
- 传输延迟:13ns
- 输出电流高,低:12mA,12mA
- 电源电压:2 V ~ 5.5 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:16-SSOP(0.209",5.30mm 宽)
- 供应商设备封装:16-SSOP
- 包装:®
- 其它名称:296-28517-6
产品特性
- 2-V to 5.5-V VCC Operation
- Maximum tpd of 11 ns at 5 V
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
- Support Mixed-Mode Voltage Operation on All Ports
- Schmitt-Trigger Circuitry on A, B, and CLR Inputs for Slow Input Transition Rates
- Edge Triggered From Active-High or Active-Low Gated Logic Inputs
- Ioff Supports Partial-Power-Down Mode Operation
- Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
- Overriding Clear Terminates Output Pulse
- Glitch-Free Power-Up Reset on Outputs
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class 11
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
The LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to
5.5-V VCC operation.These edge-triggered multivibrators feature output pulse-duration control by three
methods. In the first method, the A input is low, and the B input goes high.
In the second method, the B input is high, and the A input goes low. In the
third method, the A input is low, the B input is high, and the clear
(CLR) input goes high.The output pulse duration is programmable by selecting external resistance and
capacitance values. The external timing capacitor must be connected between
Cext and Rext/Cext (positive)
and an external resistor connected between Rext/Cext
and VCC. To obtain variable pulse durations, connect an external variable
resistance between Rext/Cext and
VCC. The output pulse duration also can be reduced by taking
CLR low.
SN74LV123ADBR 电路图

SN74LV123ADBR 电路图
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