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更新日期:2024-04-01 00:04:00

SN74AUP1G79DPWR

Texas Instruments 触发器

产品简介:低功耗单路上升沿 D 级触发器

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SN74AUP1G79DPWR 供应商

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SN74AUP1G79DPWR 中文资料属性参数

  • 现有数量:0现货9,000Factory查看交期
  • 价格:1 : ¥3.58000剪切带(CT)3,000 : ¥1.44171卷带(TR)
  • 系列:74AUP
  • 包装:卷带(TR)剪切带(CT)? 得捷定制卷带
  • 产品状态:在售
  • 功能:标准
  • 类型:D 型
  • 输出类型:非反相
  • 元件数:1
  • 每个元件位数:1
  • 时钟频率:266 MHz
  • 不同 V、最大 CL 时最大传播延迟:5.8ns @ 3.3V,30pF
  • 触发器类型:正边沿
  • 电流 - 输出高、低:4mA,4mA
  • 电压 - 供电:0.8V ~ 3.6V
  • 电流 - 静态 (Iq):500 nA
  • 输入电容:1.5 pF
  • 工作温度:-40°C ~ 85°C(TA)
  • 安装类型:表面贴装型
  • 供应商器件封装:5-X2SON(0.8x0.8)
  • 封装/外壳:4-XFDFN 裸露焊盘

产品特性

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption: ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption: Cpd = 3 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot < 10% of VCC
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22 2000-V Human-Body Model (A114-B, Class II) 1000-V Charged-Device Model (C101)
  • 2000-V Human-Body Model (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)

产品概述

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very-low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, thus resulting in an increased battery life. The AUP devices also maintain excellent signal integrity.The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup-time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.The SN74AUP1G79 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

SN74AUP1G79DPWR 电路图

SN74AUP1G79DPWR 电路图

SN74AUP1G79DPWR 电路图

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