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更新日期:2024-04-01 00:04:00

产品简介:具有施密特触发输入的单路 0.8V 至 3.6V 低功耗缓冲器

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SN74AUP1G17DPWR 供应商

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  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
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SN74AUP1G17DPWR 中文资料属性参数

  • 现有数量:2,900现货9,000Factory
  • 价格:1 : ¥4.13000剪切带(CT)3,000 : ¥1.25688卷带(TR)
  • 系列:74AUP
  • 包装:卷带(TR)剪切带(CT)? 得捷定制卷带
  • 产品状态:在售
  • 逻辑类型:缓冲器,非反向
  • 元件数:1
  • 每个元件位数:1
  • 输入类型:施密特触发器
  • 输出类型:推挽式
  • 电流 - 输出高、低:4mA,4mA
  • 电压 - 供电:0.8V ~ 3.6V
  • 工作温度:-40°C ~ 85°C(TA)
  • 安装类型:表面贴装型
  • 封装/外壳:4-XFDFN 裸露焊盘
  • 供应商器件封装:5-X2SON(0.8x0.8)

产品特性

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 222000-V Human-Body Model (A114-B, Class II)1000-V Charged-Device Model (C101)
  • 2000-V Human-Body Model (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption (Cpd = 4.4 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5.1 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications

产品概述

The AUP family of devices is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

SN74AUP1G17DPWR 电路图

SN74AUP1G17DPWR 电路图

SN74AUP1G17DPWR 电路图

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