- 封装:16-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$1.302-$2.94
更新日期:2024-04-01 00:04:00
产品简介:具有双时钟和清零功能的 4 位同步加/减二进制计数器
查看详情- 封装:16-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$1.302-$2.94
SN74ALS193AN 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
PDIP-16
2022+ -
12000
-
上海市
-
-
-
原装可开发票
SN74ALS193AN 中文资料属性参数
- 标准包装:25
- 类别:集成电路 (IC)
- 家庭:逻辑 -计数器,除法器
- 系列:74ALS
- 逻辑类型:二进制计数器
- 方向:上,下
- 元件数:1
- 每个元件的位元数:4
- 复位:异步
- 计时:同步
- 计数速率:30MHz
- 触发器类型:正边沿
- 电源电压:4.5 V ~ 5.5 V
- 工作温度:0°C ~ 70°C
- 安装类型:通孔
- 封装/外壳:16-DIP(0.300",7.62mm)
- 供应商设备封装:16-PDIP
- 包装:管件
- 其它名称:296-14722-5
产品特性
- Look-Ahead Circuitry Enhances Cascaded Counters
- Fully Synchronous in Count Modes
- Parallel Asynchronous Load for Modulo-N Count Lengths
- Asynchronous Clear
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
产品概述
The 'ALS193A are synchronous, reversible, 4-bit up/down binary
counters. Synchronous counting operation is provided by having all
flip-flops clocked simultaneously so that the outputs change
coincident with each other when instructed by the steering logic.
This mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple-clock) counters.The outputs of the four flip-flops are triggered on a
low-to-high-level transition of either count/clock (UP or DOWN)
input. The direction of the count is determined by which count input
is pulsed while the other count input is high.All four counters are fully programmable; that is, each output may
be preset to either level by placing a low on the load () input and entering the desired
data at the data inputs. The output changes to agree with the data
inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying the
count length with the preset inputs.A high level applied to the clear (CLR) input forces all outputs
to the low level. The clear function is independent of the count and
i nputs. The
UP, DOWN, and inputs are
buffered to lower the drive requirement, which significantly reduces
the loading on, or current required by, clock drivers, etc., for long
parallel words.These counters are designed to be cascaded without the need for
external circuitry. The borrow () output produces a low-level pulse while the count is
zero (all Q outputs low) and the DOWN input is low. Similarily, the
carry (CO\) output produces a low-level pulse while the count is 9 or
15 (all Q outputs high) and the UP input is low. The counters can
then be easily cascaded by feeding and to the
count-down and count-up inputs, respectively, of the succeeding
counter.The SN54ALS193A is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74ALS193A is characterized for operation from 0°C to
70°C.
SN74ALS193AN 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
4-Bit Synchronous Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
18页,701K | 查看 |
![]() |
4-Bit Synchronous Up/Down Binary Counters With Dual Clock and Clear 16-SO 0 to 70 |
18页,701K | 查看 |
![]() |
4-Bit Synchronous Up/Down Binary Counters With Dual Clock and Clear 16-SO 0 to 70 |
18页,701K | 查看 |
![]() |
4-Bit Synchronous Up/Down Binary Counters With Dual Clock and Clear 16-SO 0 to 70 |
18页,701K | 查看 |
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