- 封装:8-VDFN 裸露焊盘
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$1.215
更新日期:2024-04-01
产品简介:单通道 M-LVDS 1 类接收器
查看详情- 封装:8-VDFN 裸露焊盘
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$1.215
SN65MLVD2DRBR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI
-
SON8
24+ -
11369
-
上海市
-
-
-
上海现货
SN65MLVD2DRBR 中文资料属性参数
- 标准包装:3,000
- 类别:集成电路 (IC)
- 家庭:接口 - 驱动器,接收器,收发器
- 系列:-
- 类型:接收器
- 驱动器/接收器数:0/1
- 规程:LVDS,多点
- 电源电压:3 V ~ 3.6 V
- 安装类型:表面贴装
- 封装/外壳:8-VDFN 裸露焊盘
- 供应商设备封装:8-SON 裸露焊盘(3x3)
- 包装:带卷 (TR)
- 配用:SN65MLVD2-3EVM-ND - SN65MLVD2-3EVM
产品特性
- Low-Voltage Differential 30- Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz
- SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
- SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions
- Wide Receiver Input Common-Mode Voltage Range, -1 V to 3.4 V, Allows 2 V of Ground Noise
- Improved VIT (35 mV)
- Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology
- High Input Impedance with Low Supply Voltage
- Bus-Pin HBM ESD Protection Exceeds 9 kV
- Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC
- APPLICATIONSParallel Multipoint Data and Clock Transmission via Backplanes and CablesCellular Base StationsCentral Office SwitchesNetwork Switches and Routers
- Parallel Multipoint Data and Clock Transmission via Backplanes and Cables
- Cellular Base Stations
- Central Office Switches
- Network Switches and Routers
产品概述
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.The devices are characterized for operation from -40°C to 85°C.
SN65MLVD2DRBR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
Single Channel M-LVDS Type-1 Receiver 8-SON |
21页,737K | 查看 |
SN65MLVD2DRBR 相关产品
- 29F52SC
- AD8016ARBZ
- AD8016ARBZ-REEL
- AD8016AREZ
- AD8016AREZ-REEL
- AD8016AREZ-REEL7
- AD8018ARUZ-REEL
- AD8018ARZ-REEL7
- AD807A-155BRZRL
- AD807A-155BRZRL7
- AD8128ACPZ-R7
- AD8145WYCPZ-R7
- AD8145YCPZ-R7
- AD8392AACPZ-RL
- AD8392AAREZ
- AD8392AAREZ-RL
- ADM1181AANZ
- ADM1385ARSZ-REEL
- ADM1385ARSZ-REEL7
- ADM1485ARMZ-REEL
- ADM1485ARMZ-REEL7
- ADM1485ARZ
- ADM1485JNZ
- ADM1486AR-REEL7
- ADM1486ARZ-REEL7
- ADM1490EBRMZ-REEL7
- ADM1490EBRZ
- ADM1490EBRZ-REEL7
- ADM202EARN-REEL
- ADM202EARNZ-REEL7