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  • 封装:38-TFSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$3.497

更新日期:2024-04-01

产品简介:1:8 LVDS 时钟扇出缓冲器

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  • 封装:38-TFSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$3.497

SN65LVDS108DBTR 供应商

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SN65LVDS108DBTR 中文资料属性参数

  • 标准包装:2,000
  • 类别:集成电路 (IC)
  • 家庭:接口 - 信号缓冲器,中继器,分配器
  • 系列:65LVDS
  • 类型:转发器
  • Tx/Rx类型:LVDS
  • 延迟时间:4.5ns
  • 电容 - 输入:5pF
  • 电源电压:3 V ~ 3.6 V
  • 电流 - 电源:85mA
  • 安装类型:表面贴装
  • 封装/外壳:38-TFSOP(0.173",4.40mm 宽)
  • 供应商设备封装:38-TSSOP
  • 包装:带卷 (TR)

产品特性

  • One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater
  • Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
  • Enabling Logic Allows Individual Control of Each Driver Output, Plus All Outputs
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Load
  • Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks
  • Propagation Delay Times < 4.7 ns
  • Output Skew Less Than 300 ps and Part-to-Part Skew Less Than 1.5 ns
  • Total Power Dissipation at 200 MHz Typically Less Than 330 mW With 8 Channels Enabled
  • Driver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC < 1.5 V
  • Bus-Pin ESD Protection Exceeds 12 kV
  • Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch

产品概述

The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs.The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)The intended application of this device, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock or data distribution trees.The SN65LVDS108 is characterized for operation from –40°C to 85°C.

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