您好,欢迎来到知芯网

更新日期:2024-04-01

产品简介:具有预设和清零功能的双通道 J-K 下降沿触发器

查看详情

SN54S112J 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

SN54S112J 中文资料属性参数

  • 现有数量:0现货1,649Factory
  • 价格:在售
  • 系列:*
  • 包装:管件
  • 产品状态:在售
  • 功能:-
  • 类型:-
  • 输出类型:-
  • 元件数:-
  • 每个元件位数:-
  • 时钟频率:-
  • 不同 V、最大 CL 时最大传播延迟:-
  • 触发器类型:-
  • 电流 - 输出高、低:-
  • 电压 - 供电:-
  • 电流 - 静态 (Iq):-
  • 输入电容:-
  • 工作温度:-
  • 安装类型:-
  • 供应商器件封装:-
  • 封装/外壳:-

产品特性

  • Fully Buffered to Offer Maximum Isolation from External Disturbance
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

产品概述

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.  

SN54S112J 数据手册

数据手册 说明 数量 操作
SN54S112J

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

17 Pages页,688K 查看

IC 索引: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9