- 参考价格:¥6,541.89
更新日期:2024-04-01

产品简介:用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz
查看详情- 参考价格:¥6,541.89
SM320C6701ZMBW14 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
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TI
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-
最新批号 -
6996
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上海市
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-
SM320C6701ZMBW14 中文资料属性参数
- 制造商:Texas Instruments
- 产品种类:数字信号处理器与控制器 (DSP, DSC)
- 数据总线宽度:32 bit
- 数据 RAM 大小:128 KB
- 最大时钟频率:140 MHz
- 设备每秒兆指令数:1120 MIPs
- 工作电源电压:1.9 V, 3.3 V
- 最大工作温度:+ 115 C
- 封装 / 箱体:FCLGA
- 安装风格:SMD/SMT
- 最小工作温度:- 55 C
- 封装:Tray
- 产品:DSPs
- 工厂包装数量:1
产品特性
- Highest Performance Floating-Point Digital Signal Processor (DSP) SMJ320C6701 7-, 6-ns Instruction Cycle Time 140-, 167-MHz Clock Rate Eight 32-Bit Instructions/Cycle Up to 1 GFLOPS Performance Pin-Compatible With C6201 Fixed-Point DSP
- 7-, 6-ns Instruction Cycle Time
- 140-, 167-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Up to 1 GFLOPS Performance
- Pin-Compatible With C6201 Fixed-Point DSP
- SMJ: QML Processing to MIL-PRF-38535
- SM: Standard Processing
- Operating Temperature Ranges Extended (W) 55°C to 115°C Extended (S) 40°C to 90°C
- Extended (W) 55°C to 115°C
- Extended (S) 40°C to 90°C
- VelociTI Advanced Very Long Instruction Word (VLIW) C67x CPU Core Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional
- Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point)
- Four ALUs (Floating- and Fixed-Point)
- Two ALUs (Fixed-Point)
- Two Multipliers (Floating- and Fixed-Point)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Instruction Set Features Hardware Support for IEEE Single-Precision Instructions Hardware Support for IEEE Double-Precision Instructions Byte-Addressable (8-, 16-, 32-Bit Data) 32-Bit Address Range 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear Bit-Counting Normalization
- Hardware Support for IEEE Single-Precision Instructions
- Hardware Support for IEEE Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 32-Bit Address Range
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- 1M-Bit On-Chip SRAM 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) 512K-Bit Dual-Access Internal Data (64K Bytes)
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes)
- 32-Bit External Memory Interface (EMIF) Glueless Interface to Synchronous Memories: SDRAM and SBSRAM Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
- 16-Bit Host-Port Interface (HPI) Access to Entire Memory Map
- Access to Entire Memory Map
- Two Multichannel Buffered Serial Ports (McBSPs) Direct Interface to T1/E1, MVIP, SCSA Framers ST-Bus-Switching Compatible Up to 256 Channels Each AC97-Compatible Serial-Peripheral-Interface (SPI) Compatible (Motorola)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI) Compatible (Motorola)
- Two 32-Bit General-Purpose Timers
- Flexible Phase-Locked-Loop (PLL) Clock Generator
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- 429-Pin Ceramic Ball Grid Array (CBGA) Package (GLP Suffix) and Land Grid Array (CLGA) Package (ZMB Suffix)
- 0.18-µm/5-Level Metal Process CMOS Technology
- CMOS Technology
- 3.3-V I/Os, 1.9-V Internal
产品概述
The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.
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