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LMK04828SNKDREP

Texas Instruments 时钟发生器，PLL，频率合成器

更新日期：2024-04-01 00:04:00

LMK04828SNKDREP

Texas Instruments 时钟发生器，PLL，频率合成器

产品简介：温度范围为 -55°C 至 105°C 且符合 JESD204B 标准的超低噪声时钟抖动消除器

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LMK04828SNKDREP 供应商

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LMK04828SNKDREP 中文资料属性参数

  • 现有数量：0现货查看交期
  • 价格：2,000 : ￥272.84065卷带（TR）
  • 系列：*
  • 包装：卷带（TR）
  • 产品状态：在售
  • 类型：-
  • PLL：-
  • 输入：-
  • 输出：-
  • 电路数：-
  • 比率 - 输入:输出：-
  • 差分 - 输入:输出：-
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产品特性

  • EP Features Gold Bondwires Temperature Range: –55 to +105 °CLead Finish SnPb
  • Gold Bondwires
  • Temperature Range: –55 to +105 °C
  • Lead Finish SnPb
  • Maximum Distribution Frequency: 3.2 GHz
  • JESD204B Support
  • Ultra-Low RMS Jitter88-fs RMS Jitter (12 kHz to 20 MHz)91-fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHz
  • 88-fs RMS Jitter (12 kHz to 20 MHz)
  • 91-fs RMS Jitter (100 Hz to 20 MHz)
  • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks From PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.2 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
  • Up to 7 SYSREF Clocks
  • Maximum Clock Output Frequency 3.2 GHz
  • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
  • Up to 1 Buffered VCXO/Crystal Output From PLL1LVPECL, LVDS, 2xLVCMOS Programmable
  • LVPECL, LVDS, 2xLVCMOS Programmable
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switchover ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are Lost
  • Up to 3 Redundant Input ClocksAutomatic and Manual Switchover ModesHitless Switching and LOS
  • Automatic and Manual Switchover Modes
  • Hitless Switching and LOS
  • Integrated Low-Noise Crystal Oscillator Circuit
  • Holdover Mode When Input Clocks are Lost
  • PLL2 Normalized [1 Hz] PLL Noise Floor of –227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs
  • Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
  • Phase Detector Rate up to 155 MHz
  • OSCin Frequency-Doubler
  • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32 (Even and Odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25-ps Step Analog Delay
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)

产品概述

The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.
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LMK04828SNKDREP 电路图

LMK04828SNKDREP 电路图

LMK04828SNKDREP 电路图

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