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LMH1983SQX/NOPB

多媒体 IC
  • 参考价格:¥117.99

更新日期:2024-04-01

LMH1983SQX/NOPB

多媒体 IC

产品简介:具有音频时钟的 3G/高清/标清视频时钟发生器

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  • 参考价格:¥117.99

LMH1983SQX/NOPB 供应商

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LMH1983SQX/NOPB 中文资料属性参数

  • 制造商:National Semiconductor (TI)
  • 工作电源电压:3.3 V
  • 电源电流:100 mA
  • 最大工作温度:+ 85 C
  • 封装 / 箱体:LLP-40
  • 封装:Reel
  • 最大功率耗散:560 mW
  • 最小工作温度:- 40 C
  • 安装风格:SMD/SMT
  • 通道数量:4
  • 工厂包装数量:2500
  • 类型:Video Clock Generator

产品特性

  • Four PLLs for Simultaneous A/V Clock Generation PLL1: 27 or 13.5 MHz PLL2: 148.5 or 74.25 MHz PLL3: 148.5/1.001 or 74.25/1.001 MHz PLL4: 98.304 MHz / 2X (X = 0 to 15)
  • PLL1: 27 or 13.5 MHz
  • PLL2: 148.5 or 74.25 MHz
  • PLL3: 148.5/1.001 or 74.25/1.001 MHz
  • PLL4: 98.304 MHz / 2X (X = 0 to 15)
  • 3 x 2 Video Clock Crosspoint
  • Flexible PLL Bandwidth to Optimize Jitter Performance and Lock Time
  • Soft Resynchronization to New Reference
  • Digital Holdover or Free-run on Loss of Reference
  • Status Flags for Loss of Reference and Loss of PLL Lock
  • 3.3 V Single Supply Operation
  • I2C Interface with Address Select Pin (3 States)

产品概述

The LMH1983 is a highly-integrated programmable audio/video (A/V) clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video (SDI) and digital audio AES3/EBU standards. It offers low-jitter reference clocks for any SDI transmitter to meet stringent output jitter specifications without additional clock cleaning circuits.The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats, genlock or digital free-run modes, and override programmability of various automatic functions. The recognized input formats include HVF syncs for the major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio word clocks.The dual-stage PLL architecture integrates four PLLs with three on-chip VCOs. The first stage (PLL1) uses an external low-noise 27 MHz VCXO with narrow loop bandwidth to provide a clean reference clock for the next stage. The second stage (PLL2, 3, 4) consists of three parallel VCO PLLs for simultaneous generation of the major digital A/V clock fundamental rates, including 148.5 MHz, 148.5/1.001 MHz, and 98.304 MHz (4 × 24.576 MHz). Each PLL can generate a clock and a timing pulse to indicate top of frame (TOF).When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize to a previous reference with glitch-less operation.

LMH1983SQX/NOPB 电路图

LMH1983SQX/NOPB 电路图

LMH1983SQX/NOPB 电路图

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