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DS92LV090ATVEH

Texas Instruments 接口 IC
  • 参考价格:¥40.43-¥57.48

更新日期:2024-04-01 00:04:00

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DS92LV090ATVEH

Texas Instruments 接口 IC

产品简介:9 通道总线 LVDS 收发器

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  • 参考价格:¥40.43-¥57.48

DS92LV090ATVEH 供应商

  • 公司
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  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

DS92LV090ATVEH 中文资料属性参数

  • 制造商:National Semiconductor (TI)
  • 激励器数量:1
  • 接收机数量:1
  • 数据速率:100 Mbps
  • 工作电源电压:3.3 V
  • 最大功率耗散:1740 mW
  • 最大工作温度:+ 85 C
  • 封装 / 箱体:LQFP-64
  • 封装:Tray
  • 最小工作温度:- 40 C
  • 安装风格:SMD/SMT
  • 传播延迟时间:3.2 ns
  • 工厂包装数量:160
  • Supply Voltage - Max:3.6 V
  • Supply Voltage - Min:3 V
  • 类型:LVCMOS, LVTTL, LVDS

产品特性

  • Bus LVDS Signaling
  • 3.2 Nanosecond Propagation Delay Max
  • Chip to Chip Skew ±800ps
  • Low Power CMOS Design
  • High Signaling Rate Capability (Above 100 Mbps)
  • 0.1V to 2.3V Common Mode Range for VID = 200mV
  • ±100 mV Receiver Sensitivity
  • Supports Open and Terminated Failsafe on Port Pins
  • 3.3V Operation
  • Glitch Free Power Up/Down (Driver & Receiver Disabled)
  • Light Bus Loading (5 pF Typical) per Bus LVDS Load
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Product Offered in 64 Pin LQFP Package
  • High Impedance Bus Pins on Power off (VCC = 0V)
  • Driver Channel to Channel Skew (Same Device) 230ps Typical
  • Receiver Channel to Channel Skew (Same Device) 370ps Typical

产品概述

The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Section for more details.)

DS92LV090ATVEH 数据手册

数据手册 说明 数量 操作
DS92LV090ATVEH

9 Channel Bus LVDS Transceiver

9 Pages页,171K 查看
DS92LV090ATVEH/NOPB

9/9 Transceiver Half LVDS 64-TQFP (10x10)

16页,931K 查看

DS92LV090ATVEH 电路图

DS92LV090ATVEH 电路图

DS92LV090ATVEH 电路图

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