- 参考价格:¥23.39-¥24.29
更新日期:2024-04-01 00:04:00
产品简介:+3.3V 可编程 LVDS 发送器 18 位平板显示链路 - 87.5MHz
查看详情- 参考价格:¥23.39-¥24.29
DS90C365AMTX 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
National Semiconductor
-
TSSOP48
21+ -
14991
-
上海市
-
-
-
一级代理原装
-
TI/NS
-
TSSOP48
21+ -
4000
-
上海市
-
-
-
原装现货,品质为先,请来电垂询!
-
TI
-
TSSOP48
22+ -
300000
-
常州
-
-
-
原装正品
-
NS
-
TSSOP
23+ -
5800
-
上海市
-
-
-
进口原装现货,杜绝假货。
-
NSC/ELNAF
-
TSSOP
1801+ -
15000
-
上海市
-
-
-
原装现货,精专配套,正品BOM表报价
-
TI
-
TSSOP
23+ -
46000
-
合肥
-
-
-
科大讯飞战略投资企业,提供一站式配套服务
-
TI/德州仪器
-
TSSOP48
21+ -
10000
-
杭州
-
-
-
全新原装,价格优势
-
TI/德州仪器
-
TSSOP48
17+ -
1004
-
上海市
-
-
-
原装可开发票
DS90C365AMTX 中文资料属性参数
- 制造商:National Semiconductor (TI)
- 激励器数量:3
- 接收机数量:21
- 数据速率:612.5 Mbps
- 工作电源电压:3.3 V
- 最大功率耗散:1980 mW
- 最大工作温度:+ 70 C
- 封装 / 箱体:TSSOP-48
- 封装:Reel
- 最小工作温度:- 10 C
- 安装风格:SMD/SMT
- Supply Voltage - Max:3.6 V
- Supply Voltage - Min:3 V
- 类型:LVDS
产品特性
- Pin-to-pin compatible to DS90C363, DS90C363A and DS90C365
- No special start-up sequence required between clock/data and /PD pins. Input signals (clock and data) can be applied either before or after the device is powered.
- Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread.
- “Input Clock Detection” feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high.
- 18 to 87.5 MHz shift clock support
- Tx power consumption < 146 mW (typ) at 87.5 MHz Grayscale
- Tx Power-down mode < 37 uW (typ)
- Supports VGA, SVGA, XGA, SXGA (dual pixel), SXGA+ (dual pixel), UXGA (dual pixel).
- Narrow bus reduces cable size and cost
- Up to 1.785 Gbps throughput
- Up to 223.125 Megabytes/sec bandwidth
- 345 mV (typ) swing LVDS devices for low EMI
- PLL requires no external components
- Compliant to TIA/EIA-644 LVDS standard
- Low profile 48-lead TSSOP package
产品概述
The DS90C365A is a pin to pin compatible replacement for DS90C363, DS90C363A and
DS90C365. The DS90C365A has additional features and improvements making it an ideal replacement for
DS90C363, DS90C363A and DS90C365. family of LVDS Transmitters.The DS90C365A transmitter converts 21 bits of LVCMOS/LVTTL data into four LVDS (Low
Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over the fourth LVDS link. Every cycle of the transmit clock 21 bits
RGB of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 21 bits
of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a
rate of 612.5 Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 229.687
Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe
through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a
Falling edge strobe FPDLink Receiver without any translation logic.This chipset is an ideal means to solve EMI and cable size problems associated with wide,
high-speed TTL interfaces with added Spead Spectrum Clocking support..
DS90C365AMTX 电路图
DS90C365AMTX 电路图
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