- 参考价格:¥38.30-¥39.05
更新日期:2024-04-01 00:04:00
产品简介:5MHz 至 35MHz 直流平衡 24 位 FPD-Link II 串行器
查看详情- 参考价格:¥38.30-¥39.05
DS90C241IVSX/NOPB 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TQFP-48(7x7)
2022+ -
12000
-
上海市
-
-
-
原装可开发票
DS90C241IVSX/NOPB 中文资料属性参数
- 制造商:National Semiconductor (TI)
- 激励器数量:1
- 接收机数量:24
- 工作电源电压:3.3 V
- 最大工作温度:+ 105 C
- 封装 / 箱体:TQFP-48
- 封装:Reel
- 最小工作温度:- 40 C
- 安装风格:SMD/SMT
- 工厂包装数量:1000
- Supply Voltage - Max:3.6 V
- Supply Voltage - Min:3 V
- 类型:LVDS
产品特性
- 5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
- User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
- User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
- Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
- Individual Power-Down Controls for Both Transmitter and Receiver
- Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
- All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
- LOCK Output Flag to Ensure Data Integrity at Receiver Side
- Balanced TSETUP and THOLD Between RCLK and RDATA on Receiver Side
- PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
- All LVCMOS Inputs and Control Pins Have Internal Pulldown
- On-Chip Filters for PLLs on Transmitter and Receiver
- Temperature Range: –40°C to 105°C
- Greater Than 8-kV HBM ESD Tolerant
- Meets AEC-Q100 Compliance
- Power Supply Range: 3.3 V ± 10%
- 48-Pin TQFP Package
产品概述
The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully
transparent data and control LVDS serial stream with embedded clock information. This single serial
stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew
problems between parallel data and clock paths. It saves system cost by narrowing data paths, which
in turn reduces PCB layers, cable width, and connector size and pins.The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides
a low-power and low-noise environment for reliably transferring data over a serial transmission
path. By optimizing the serializer output edge rate for the operating frequency range, EMI is
further reduced.In addition, the device features pre-emphasis to boost signals over longer distances
using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled
interconnects.
DS90C241IVSX/NOPB 电路图
DS90C241IVSX/NOPB 电路图
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