DM3725CUS100_DM3725CUS100中文资料_价格

DM3725CUS100 供应商

公司
型号
品牌
封装/批号
数量
地区
日期
说明
询价

上海三崧电子有限公司 保2千
DM3725CUS100
TI
原厂原装
22+
3288
上海市
-
一级代理原装

上海旋尔电子有限公司
DM3725CUS100
Texas Instruments
原厂原装
22+授权代理
15800
上海市
-
旋尔只做进口原装，假一赔十...

上海鑫勃源电子科技有限公司
DM3725CUS100
TI
原厂原封装
新批号
887000
上海市
-
原厂发货进口原装微信同步QQ893727827

安徽芯海技术有限公司
DM3725CUS100
TI
原厂原装
2318+
9200
合肥
-
科大讯飞战略投资企业

DM3725CUS100 中文资料属性参数

制造商：Texas Instruments
产品种类：数字信号处理器与控制器 (DSP, DSC)
核心：ARM Cortex A8+C64x
芯体结构：RISC+VLIW
系列：DaVinci DM37
系列/芯体：DaVinci DM37
工厂包装数量：90
类型：DaVinci DM37

产品特性

DM3730, DM3725 Digital Media Processors: Compatible with OMAP™ 3 Architecture ARM® microprocessor (MPU) Subsystem Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz NEON SIMD Coprocessor High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem Up to 800-MHz TMS320C64x+™ DSP Core Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) Video Hardware Accelerators POWER SGX™ Graphics Accelerator (DM3730 only) Tile Based Acrchitecture Delivering up to 20 MPoly/sec Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 Fine Grained Task Switching, Load Balancing, and Power Management Programmable High Quality Image Anti-Aliasing Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core Eight Highly Independent Functional Units Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x+™ Enhancements Protected Mode Operation Expectations Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Operation C64x+TM L1/L2 Memory Architecture
Compatible with OMAP™ 3 Architecture
ARM® microprocessor (MPU) Subsystem Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz NEON SIMD Coprocessor
Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz
NEON SIMD Coprocessor
High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem Up to 800-MHz TMS320C64x+™ DSP Core Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) Video Hardware Accelerators
Up to 800-MHz TMS320C64x+™ DSP Core
Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
Video Hardware Accelerators
POWER SGX™ Graphics Accelerator (DM3730 only) Tile Based Acrchitecture Delivering up to 20 MPoly/sec Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 Fine Grained Task Switching, Load Balancing, and Power Management Programmable High Quality Image Anti-Aliasing
Tile Based Acrchitecture Delivering up to 20 MPoly/sec
Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
Fine Grained Task Switching, Load Balancing, and Power Management
Programmable High Quality Image Anti-Aliasing
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core Eight Highly Independent Functional Units Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x+™ Enhancements Protected Mode Operation Expectations Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Operation
Eight Highly Independent Functional Units
Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle
Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle
Load-Store Architecture With Non-Aligned Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Additional C64x+™ Enhancements Protected Mode Operation Expectations Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Operation
Protected Mode Operation
Expectations Support for Error Detection and Program Redirection
Hardware Support for Modulo Loop Operation
C64x+TM L1/L2 Memory Architecture

产品概述

The DM37x generation of high-performance, applications processors are based on the enhanced device architecture and are integrated on TI's advanced 45-nm process technology. This architecture is designed to provide best in class ARM and Graphics performance while delivering low power consumption. This balance of performance and power allow the device to support the following example applications:The device can support numerous HLOS and RTOS solutions including Linux and Windows Embedded CE which are available directly from TI. Additionally, the device is fully backward compatible with previous Cortex™-A8 processors and OMAP™ processors.This DM3730/25 Digital Media Processor data manual presents the electrical and mechanical specifications for the DM3730/25 Applications Processor. The information contained in this data manual applies to both the commercial and extended temperature versions of the DM3730/25 Digital Media Processor unless otherwise indicated. It consists of the following sections:

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DM3725CUS100 数据手册

数据手册	说明	数量	操作
DM3725CUS100	IC DGTL MEDIA PROCESSOR 423FCBGA	280页,3.22M	查看

DM3725CUS100 电路图

DM3725CUS100