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  • 封装:64-VFQFN 裸露焊盘
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$34.1

更新日期:2024-04-01

产品简介:16 位、1.0GSPS 数模转换器 (DAC)

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  • 封装:64-VFQFN 裸露焊盘
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$34.1

DAC5681IRGCR 供应商

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DAC5681IRGCR 中文资料属性参数

  • 产品培训模块:Data Converter Basics
  • 标准包装:2,000
  • 类别:集成电路 (IC)
  • 家庭:数据采集 - 数模转换器
  • 系列:-
  • 设置时间:10.4ns
  • 位数:16
  • 数据接口:LVDS,并联,串行
  • 转换器数目:1
  • 电压电源:模拟和数字
  • 功率耗散(最大):650mW
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:64-VFQFN 裸露焊盘
  • 供应商设备封装:64-VQFN 裸露焊盘(9x9)
  • 包装:带卷 (TR)
  • 输出数目和类型:2 电流,单极
  • 采样率(每秒):1G

产品特性

  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus 8 Sample Input FIFO On-Chip Delay Lock Loop
  • 8 Sample Input FIFO
  • On-Chip Delay Lock Loop
  • High Performance 73 dBc ACLR WCDMA TM1 at 180 MHz
  • 73 dBc ACLR WCDMA TM1 at 180 MHz
  • On Chip 1.2 V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-Pin 9 × 9 mm QFN

产品概述

The DAC5681 is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input and internal voltage reference. The DAC5681 offers superior linearity and noise performance.The DAC5681 integrates a wideband LVDS port with on-chip termination, providing full 1.0 GSPS data transfer into the DAC and lower EMI than traditional CMOS data interfaces. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.The current-steering architecture of the DAC5681 consists of a segmented array of current sinking switches directing up to 20mA of full-scale current to complementary output nodes. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.The DAC5681 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. The device is pin upgradeable to the other members of the family: the DAC5681Z and DAC5682Z. The single-channel DAC5681Z and dual-channel DAC5682Z both provide optional 2x/4x interpolation and a clock multiplying PLL.

DAC5681IRGCR 电路图

DAC5681IRGCR 电路图

DAC5681IRGCR 电路图

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