- 封装:24-SSOP(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$2.234
更新日期:2024-04-01 00:04:00
产品简介:Direct Rambus? 时钟发生器
查看详情- 封装:24-SSOP(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$2.234
CDCR83ADBQR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
SSOP/QSOP-24
2022+ -
12000
-
上海市
-
-
-
原装可开发票
-
TI
-
TSSOP
23+ -
46000
-
合肥
-
-
-
科大讯飞战略投资企业,提供一站式配套服务
-
TI
-
SSOP-24
4 -
1678
-
杭州
-
-
-
原装正品现货
CDCR83ADBQR 中文资料属性参数
- 标准包装:2,500
- 类别:集成电路 (IC)
- 家庭:时钟/计时 - 专用
- 系列:-
- 类型:时钟/频率发生器,多路复用器
- PLL:是
- 主要目的:存储器,RDRAM
- 输入:TTL
- 输出:时钟
- 电路数:1
- 比率 - 输入:输出:1:1
- 差分 - 输入:输出:无/是
- 频率 - 最大:400MHz
- 电源电压:3.135 V ~ 3.465 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:24-SSOP(0.154",3.90mm 宽)
- 供应商设备封装:24-SSOP/QSOP
- 包装:带卷 (TR)
产品特性
- 400-MHz Differential Clock Source for Direct Rambus™ Memory Systems for an 800-MHz Data Transfer Rate
- Fail-Safe Power Up Initialization
- Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock
- Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications
- Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ)
- Packaged in a Shrink Small-Outline Package (DBQ)
- Supports Frequency Multipliers: 4, 6, 8, 16/3
- No External Components Required for PLL
- Supports Independent Channel Clocking
- Spread Spectrum Clocking Tracking Capability to Reduce EMI
- Designed for Use With TIs 133-MHz Clock Synthesizers CDC924 and CDC921
- Cycle-Cycle Jitter Is Less Than 50 ps at 400 MHz
- Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement
- Supports Industrial Temperature Range of 40°C to 85°C
产品概述
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or
processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile
PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory
applications.The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable
synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus
memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and
memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs
and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies
by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase
difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between
PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary
without incurring additional latency.User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one
of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz with
clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass
mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where
synchronization between the Rambus clock and a system clock is not required. Test modes are provided to
bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state
for board testing.The CDCR83A has a fail-safe power up initialization state-machine which supports proper operation under all
power up conditions.The CDCR83A is characterized for operation over free-air temperatures of 40°C to 85°C.
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