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  • 封装:64-BGA
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:托盘
  • 参考价格:$13.8-$23

更新日期:2024-04-01 00:04:00

产品简介:高性能、低相位噪声、低偏移的时钟同步器(使参考时钟与 VCXO 同步)

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  • 封装:64-BGA
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:托盘
  • 参考价格:$13.8-$23

CDC7005ZVA 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CDC7005ZVA 中文资料属性参数

  • 标准包装:348
  • 类别:集成电路 (IC)
  • 家庭:时钟/计时 - 时钟发生器,PLL,频率合成器
  • 系列:-
  • 类型:时钟同步器和抖动消除器
  • PLL:
  • 输入:LVCMOS,LVPECL
  • 输出:LVPECL
  • 电路数:1
  • 比率 - 输入:输出:2:5
  • 差分 - 输入:输出:是/是
  • 频率 - 最大:800MHz
  • 除法器/乘法器:是/是
  • 电源电压:3 V ~ 3.6 V
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:64-BGA
  • 供应商设备封装:64-BGA(8x8)
  • 包装:托盘
  • 配用:296-31329-ND - KIT WIDEBAND DGTL REPEATER DEMO296-20836-ND - EVALUATION MOD FOR CDCM7005-QFN296-20835-ND - EVALUATION MOD FOR CDCM7005-BGA296-20834-ND - EVALUATION MOD FOR CDC7005-QFN296-17044-ND - EVAL BOARD FOR CDC7005 SERIES
  • 其它名称:296-26035CDC7005ZVA-ND

产品特性

  • High Performance 1:5 PLL Clock Synchronizer
  • Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
  • Synchronizes Frequencies up to 800 MHz (VCXO_IN)
  • Supports Five Differential LVPECL Outputs
  • Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
  • All Outputs Are Synchronized
  • Integrated Low-Noise OPA for External Low-Pass Filter
  • Efficient Jitter Screening From Low PLL Loop Bandwidth
  • Low-Phase Noise Characteristic
  • Programmable Delay for Phase Adjustments
  • Predivider Loop BW Adjustment
  • SPI Controllable Division Setting
  • Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
  • 3.3-V Power Supply
  • Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C

产品概述

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.The CDC7005 is characterized for operation from –40°C to 85°C.

CDC7005ZVA 数据手册

数据手册 说明 数量 操作
CDC7005ZVA

3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

29 Pages页,409K 查看
CDC7005ZVAR

3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

29 Pages页,409K 查看
CDC7005ZVAT

3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

29 Pages页,409K 查看
CDC7005ZVAT

IC CLK SYNC/JITTER CLEANER 64BGA

34页,1.08M 查看

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