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  • 封装:16-TSSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$0.2475-$0.62

更新日期:2024-04-01 00:04:00

产品简介:带 VCO 的高速 CMOS 逻辑锁相环

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  • 封装:16-TSSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$0.2475-$0.62

CD74HC4046APWR 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD74HC4046APWR 中文资料属性参数

  • 标准包装:1
  • 类别:集成电路 (IC)
  • 家庭:时钟/计时 - 时钟发生器,PLL,频率合成器
  • 系列:74HC
  • 类型:锁相环路(PLL)
  • PLL:
  • 输入:CMOS
  • 输出:CMOS
  • 电路数:1
  • 比率 - 输入:输出:1:4
  • 差分 - 输入:输出:无/无
  • 频率 - 最大:38MHz
  • 除法器/乘法器:无/无
  • 电源电压:2 V ~ 6 V
  • 工作温度:-55°C ~ 125°C
  • 安装类型:表面贴装
  • 封装/外壳:16-TSSOP(0.173",4.40mm 宽)
  • 供应商设备封装:16-TSSOP
  • 包装:®
  • 其它名称:296-9210-6

产品特性

  • Operating Frequency Range Up to 18MHz (Typ) at VCC = 5V Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Up to 18MHz (Typ) at VCC = 5V
  • Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Choice of Three Phase Comparators EXCLUSIVE-OR Edge-Triggered JK Flip-Flop Edge-Triggered RS Flip-Flop
  • EXCLUSIVE-OR
  • Edge-Triggered JK Flip-Flop
  • Edge-Triggered RS Flip-Flop
  • Excellent VCO Frequency Linearity
  • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
  • Minimal Frequency Drift
  • Operating Power Supply Voltage Range VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
  • VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
  • Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
  • Fanout (Over Temperature Range) Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications FM Modulation and Demodulation Frequency Synthesis and Multiplication Frequency Discrimination Tone Decoding Data Synchronization and Conditioning Voltage-to-Frequency Conversion Motor-Speed Control
  • FM Modulation and Demodulation
  • Frequency Synthesis and Multiplication
  • Frequency Discrimination
  • Tone Decoding
  • Data Synchronization and Conditioning
  • Voltage-to-Frequency Conversion
  • Motor-Speed Control

产品概述

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

CD74HC4046APWR 数据手册

数据手册 说明 数量 操作
CD74HC4046APWR

High-Speed CMOS Logic Phase-Locked Loop with VCO

28 Pages页,439K 查看
CD74HC4046APWRE4

High-Speed CMOS Logic Phase-Locked Loop with VCO

28 Pages页,439K 查看

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