CD54HCT175F3A
触发器更新日期:2024-04-01
CD54HCT175F3A 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
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DIP-16
2019+ -
5800
-
上海市
-
-
-
全新原装现货
-
TI
-
DIP
22+ -
5000
-
常州
-
-
-
全新原装现货热卖
-
TI
-
CDIP
23+ -
5800
-
上海市
-
-
-
进口原装现货,杜绝假货。
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TI H
-
DIP
- -
7
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台州
-
-
CD54HCT175F3A 中文资料属性参数
- 现有数量:0现货4,939Factory
- 价格:在售
- 系列:*
- 包装:管件
- 产品状态:在售
- 功能:-
- 类型:-
- 输出类型:-
- 元件数:-
- 每个元件位数:-
- 时钟频率:-
- 不同 V、最大 CL 时最大传播延迟:-
- 触发器类型:-
- 电流 - 输出高、低:-
- 电压 - 供电:-
- 电流 - 静态 (Iq):-
- 输入电容:-
- 工作温度:-
- 安装类型:-
- 供应商器件封装:-
- 封装/外壳:-
产品特性
- Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
- Positive Edge Pulse Triggering
- Complementary Outputs
- Buffered Inputs
- Fanout (Over Temperature Range) Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il 1µA at VOL, VOH
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
产品概述
The HC175 and HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.
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