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CD54HC4520F3A

Texas Instruments 计数器，除法器

更新日期：2024-04-01

CD54HC4520F3A

Texas Instruments 计数器，除法器

产品简介：高速 CMOS 逻辑双路二进制加法计数器

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CD54HC4520F3A 供应商

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CD54HC4520F3A 中文资料属性参数

  • 现有数量：0现货2,019Factory
  • 价格：在售
  • 系列：*
  • 包装：管件
  • 产品状态：在售
  • 逻辑类型：-
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产品特性

  • Positive or Negative Edge Triggering
  • Synchronous Internal Carry Propagation
  • Fanout (Over Temperature Range) Standard Outputs...10 LSTTL Loads Bus Driver Outputs...15 LSTTL Loads
  • Standard Outputs...10 LSTTL Loads
  • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il 1µA at VOL, VOH
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il 1µA at VOL, VOH

产品概述

The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3 to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.
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CD54HC4520F3A 数据手册

数据手册 说明 数量 操作
CD54HC4520F3A

High-Speed CMOS Logic Dual Synchronous Counters

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