- 封装:16-SOIC(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$0.158
更新日期:2024-04-01
产品简介:CMOS 双路 BCD 加法计数器
查看详情- 封装:16-SOIC(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$0.158
CD4518BM96 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI
-
SOP-16
- -
4140
-
上海市
-
-
-
经营22年实体店原装,具体年份和数量以实际为准
-
TI/德州仪器
-
SOP
21+ -
3000
-
杭州
-
-
-
只做原装现货,大量现货热卖
-
TI(德州仪器)
-
SOIC-16
2022+ -
12000
-
上海市
-
-
-
原装可开发票
CD4518BM96 中文资料属性参数
- 标准包装:2,500
- 类别:集成电路 (IC)
- 家庭:逻辑 -计数器,除法器
- 系列:4000B
- 逻辑类型:BCD 计数器
- 方向:上
- 元件数:2
- 每个元件的位元数:4
- 复位:异步
- 计时:同步
- 计数速率:8MHz
- 触发器类型:正,负
- 电源电压:3 V ~ 18 V
- 工作温度:-55°C ~ 125°C
- 安装类型:表面贴装
- 封装/外壳:16-SOIC(0.154",3.90mm 宽)
- 供应商设备封装:16-SOIC N
- 包装:带卷 (TR)
产品特性
- Medium-speed operation - 6-MHz typical clock frequency at 10 V
- Positive- or negative-edge triggering
- Synchronous internal carry propagation
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package-temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices"
- Applications Multistage synchronous counting Multistage ripple counting Frequency dividers
- Multistage synchronous counting
- Multistage ripple counting
- Frequency dividers
产品概述
CD4518 Dual BCD Up-Counter and CD4520 Dual Binary Up-Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.The CD4518B and CD4520B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4518BM96 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
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CMOS DUAL UP-COUNTERS |
13 Pages页,557K | 查看 |
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CMOS Dual BCD Up-Counter 16-SOIC -55 to 125 |
16页,733K | 查看 |
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