- 封装:16-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.1785-$0.5
更新日期:2025-02-12
产品简介:CMOS 可预置二进制加/减计数器
查看详情- 封装:16-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.1785-$0.5
CD4516BPWR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
CD4516BPWR
原装现货 -
TI
-
TSSOP-16
2210 -
28000
-
北京市
-
02-12
-
原厂授权渠道,现货
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TSSOP-16
2022+ -
12000
-
上海市
-
-
-
原装可开发票
-
TI
-
TSSOP-16
新批号 -
887000
-
上海市
-
-
-
原厂直发进口原装微信同步QQ893727827
CD4516BPWR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 -计数器,除法器
- 系列:4000B
- 逻辑类型:二进制计数器
- 方向:上,下
- 元件数:1
- 每个元件的位元数:4
- 复位:异步
- 计时:同步
- 计数速率:11MHz
- 触发器类型:正边沿
- 电源电压:3 V ~ 18 V
- 工作温度:-55°C ~ 125°C
- 安装类型:表面贴装
- 封装/外壳:16-TSSOP(0.173",4.40mm 宽)
- 供应商设备封装:16-TSSOP
- 包装:®
- 其它名称:296-3530-6
产品特性
- Medium-speed operation - fCL = 8 NHz typ. at 10 V
- Synchronous internal carry propagation
- Reset and Preset capability
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices"
- Applications: Up/Down difference counting Multistage synchronous counting Multistage ripple counting Synchronous frequency dividers
- Up/Down difference counting
- Multistage synchronous counting
- Multistage ripple counting
- Synchronous frequency dividers
产品概述
CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode.If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage.The CD4510B and CD4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. (See Fig.15).These devices are similar to types MC14510 and MC14516.The CD4510B and CD4516B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4516B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).
CD4516BPWR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
CMOS PRESETTABLE UP/DOWN COUNTERS |
12 Pages页,538K | 查看 |
![]() |
CMOS Presettable Binary Up/Down Counter 16-TSSOP -55 to 125 |
15页,715K | 查看 |
![]() |
CMOS Presettable Binary Up/Down Counter 16-TSSOP -55 to 125 |
15页,715K | 查看 |
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