CD4516BF
计数器,除法器更新日期:2024-04-01
CD4516BF 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
Harris
-
CDIP16
21+ -
2
-
上海市
-
-
-
一级代理原装
-
H
-
DIP
- -
4
-
台州
-
-
-
TI
-
PQFP
8 -
5500
-
杭州
-
-
-
原装正品现货
-
TI
-
-
2019+ -
5800
-
上海市
-
-
-
全新原装现货
-
TI
-
标准封装
23+ -
15000
-
上海市
-
-
-
中国区代理原装现货特价热卖
CD4516BF 中文资料属性参数
- 现有数量:0现货1,669Factory
- 价格:在售
- 系列:-
- 包装:管件
- 产品状态:在售
- 逻辑类型:二进制计数器
- 方向:上,下
- 元件数:1
- 每个元件位数:4
- 复位:异步
- 定时:同步
- 计数速率:11 MHz
- 触发器类型:正边沿
- 电压 - 供电:3 V ~ 18 V
- 工作温度:-55°C ~ 125°C(TA)
- 安装类型:通孔
- 封装/外壳:16-CDIP(0.300",7.62mm)
- 供应商器件封装:16-CDIP
产品特性
- Medium-speed operation - fCL = 8 NHz typ. at 10 V
- Synchronous internal carry propagation
- Reset and Preset capability
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices"
- Applications: Up/Down difference counting Multistage synchronous counting Multistage ripple counting Synchronous frequency dividers
- Up/Down difference counting
- Multistage synchronous counting
- Multistage ripple counting
- Synchronous frequency dividers
产品概述
CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode.If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage.The CD4510B and CD4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. (See Fig.15).These devices are similar to types MC14510 and MC14516.The CD4510B and CD4516B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4516B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).
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