CD4081BM

Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

产品概述

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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CD4081BM 数据手册

数据手册	说明	数量	操作
CD4081BM96	CMOS AND GATES	12 Pages页,531K	查看
CD4081BM96E4	CMOS Quad 2-Input AND Gate 14-SOIC -55 to 125	16页,711K	查看
CD4081BM96G4	CMOS Quad 2-Input AND Gate 14-SOIC -55 to 125	16页,711K	查看
CD4081BME4	CMOS Quad 2-Input AND Gate 14-SOIC -55 to 125	16页,711K	查看
CD4081BMG4	CMOS Quad 2-Input AND Gate 14-SOIC -55 to 125	16页,711K	查看
CD4081BMJ	Quad 2-Input OR, AND Buffered B Series Gate	8 Pages页,183K	查看
CD4081BMN	Quad 2-Input OR, AND Buffered B Series Gate	8 Pages页,183K	查看
CD4081BMS	CMOS AND Gate	10 Pages页,114K	查看
CD4081BMT	CMOS AND GATES	12 Pages页,531K	查看
CD4081BMT	AND Gate IC 4 Channel 14-SOIC	29页,1.39M	查看

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CD4081BM

CD4081BM

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CD4081BM 中文资料属性参数

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产品概述

CD4081BM 数据手册

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