更新日期:2024-04-01
产品简介:军用 3 通道、3 输入、3V 至 18V 或门
查看详情CD4075BF3A 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
-
4 -
50
-
杭州
-
-
-
原装正品现货
-
TI
-
-
2019+ -
5800
-
上海市
-
-
-
全新原装现货
-
TI
-
标准封装
23+ -
15000
-
上海市
-
-
-
中国区代理原装现货特价热卖
-
TI
-
DIP
22+ -
5000
-
常州
-
-
-
原装现货热卖
CD4075BF3A 中文资料属性参数
- 现有数量:0现货4,457Factory
- 价格:在售
- 系列:4000B
- 包装:管件
- 产品状态:在售
- 逻辑类型:或门
- 电路数:3
- 输入数:3
- 特性:-
- 电压 - 供电:3V ~ 18V
- 电流 - 静态(最大值):5 μA
- 电流 - 输出高、低:6.8mA,6.8mA
- 逻辑电平 - 低:1.5V ~ 4V
- 逻辑电平 - 高:3.5V ~ 11V
- 不同 V、最大 CL 时最大传播延迟:90ns @ 15V,50pF
- 工作温度:-55°C ~ 125°C
- 安装类型:通孔
- 供应商器件封装:14-CDIP
- 封装/外壳:14-CDIP(0.300",7.62mm)
产品特性
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Standardized, symmetrical output characteristics
- Noise margin (full package-temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices"
产品概述
CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic
OR function and supplement the existing family of CMOS gates.The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),
14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead
thin shrink small-outline packages (PW and PWR suffixes).
CD4075BF3A 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
CMOS OR GATES |
12 Pages页,525K | 查看 |
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