更新日期:2024-04-01
产品简介:具有三态输出的 CMOS 四路与非 R/S 锁存器
查看详情CD4044BF 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
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TI
-
DIP
22+ -
5000
-
常州
-
-
-
原装现货热卖
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TI
-
DIP
23+ -
5800
-
上海市
-
-
-
进口原装现货,杜绝假货。
-
TI
-
DIP
2213 -
8
-
台州
-
-
-
TI
-
-
8 -
5500
-
杭州
-
-
-
原装正品现货
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HAR
-
-
2019+ -
5800
-
上海市
-
-
-
全新原装现货
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Harris
-
CDIP16
21+ -
12
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上海市
-
-
-
一级代理原装
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TI厂商
-
模块
23+ -
15000
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上海市
-
-
-
中国区代理原装特价热卖
CD4044BF 中文资料属性参数
- 现有数量:0现货1,910Factory
- 价格:在售
- 系列:4000B
- 包装:管件
- 产品状态:在售
- 逻辑类型:S-R 锁存器
- 电路:4:4
- 输出类型:三态,非反相
- 电压 - 供电:3V ~ 18V
- 独立电路:1
- 延迟时间 - 传播:50ns @ 15V,50pF
- 电流 - 输出高、低:6.8mA,6.8mA
- 工作温度:-55°C ~ 125°C
- 安装类型:通孔
- 封装/外壳:16-CDIP(0.300",7.62mm)
- 供应商器件封装:16-CDIP
产品特性
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications Holding register in multi-register system Four bits of independent storage with output ENABLE Strobed register General digital logic CD4043B for positive logic systems CD4044B for negative logic systems
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4043B for positive logic systems
- CD4044B for negative logic systems
产品概述
CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4044BF 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
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CMOS QUAD 3-STATE R/S LATCHES |
13 Pages页,591K | 查看 |
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CMOS QUAD 3-STATE R/S LATCHES |
13 Pages页,582K | 查看 |
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