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更新日期:2024-04-01

产品简介:具有 8 个解码输出的 CMOS 十进制计数器

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CD4022BF3A 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD4022BF3A 中文资料属性参数

  • 现有数量:0现货1,843Factory
  • 价格:在售
  • 系列:4000B
  • 包装:管件
  • 产品状态:在售
  • 逻辑类型:二进制计数器
  • 方向:
  • 元件数:1
  • 每个元件位数:4
  • 复位:异步
  • 定时:-
  • 计数速率:11 MHz
  • 触发器类型:正边沿
  • 电压 - 供电:3 V ~ 18 V
  • 工作温度:-55°C ~ 125°C(TA)
  • 安装类型:通孔
  • 封装/外壳:16-CDIP(0.300",7.62mm)
  • 供应商器件封装:16-CDIP

产品特性

  • Fully static operation
  • Medium speed operation…10 MHz (typ.) at VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications: Decade counter/decimal decode display (CD4017B) Binary counter/decoder Frequency division Counter control/timers Divde-by-N counting For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"
  • Decade counter/decimal decode display (CD4017B)
  • Binary counter/decoder
  • Frequency division
  • Counter control/timers
  • Divde-by-N counting
  • For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"

产品概述

CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT siganl is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes on cycle every 10 clock input cycles in the CD4017B or every 8 clock input cycles in the CD4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.The CD4017B and CD4022B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4017B types also are supplied in 16-lead small-outline packages (M and M96 suffixes).

CD4022BF3A 数据手册

数据手册 说明 数量 操作
CD4022BF3A

CMOS COUNTER/DIVIDERS

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