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  • 封装:16-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.1593-$0.56

更新日期:2024-04-01

产品简介:CMOS 可预置 BCD 加/减计数器(具有重置功能的双时钟)

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  • 封装:16-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.1593-$0.56

CD40192BE 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD40192BE 中文资料属性参数

  • 标准包装:25
  • 类别:集成电路 (IC)
  • 家庭:逻辑 -计数器,除法器
  • 系列:4000B
  • 逻辑类型:计数器,十进制
  • 方向:上,下
  • 元件数:1
  • 每个元件的位元数:4
  • 复位:异步
  • 计时:同步
  • 计数速率:5.5MHz
  • 触发器类型:正边沿
  • 电源电压:3 V ~ 18 V
  • 工作温度:-55°C ~ 125°C
  • 安装类型:通孔
  • 封装/外壳:16-DIP(0.300",7.62mm)
  • 供应商设备封装:16-PDIP
  • 包装:管件
  • 其它名称:296-3509-5

产品特性

  • Individual clock lines for counting up or counting down
  • Synchronous high-speed carry and borrow propagation delays for cascading
  • Asynchronous reset and preset capability
  • Medium-speed operation–fCL = 8MHz (typ.) @ 10 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications: Up/down difference counting Multistage ripple counting Synchronous frequency dividers A/D and D/A conversion Programmable binary or BCD counting
  • Up/down difference counting
  • Multistage ripple counting
  • Synchronous frequency dividers
  • A/D and D/A conversion
  • Programmable binary or BCD counting

产品概述

CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\ ENABLE\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\ and BORROW\ outputs for multiple-stage counting schemes are provided.The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\ ENABLE\ control is low.The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down on count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high.The CARRY\ and BORROW\ signals are high with the counter is counting up or down. The CARRY\ signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW\ signal goes low one-half clock cycle after the counter reaches its minimum count in the count-down mode. Cascading of multiple packages is easily accomplished with out the need for additional external circuitry by tying the BORROW\ and CARRY\ outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package.The CD40192B and CD40193B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40192BE 数据手册

数据手册 说明 数量 操作
CD40192BEE4

CMOS Presettable BCD Up/Down Counter (Dual Clock with Reset) 16-PDIP -55 to 125

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