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  • 封装:16-SOIC(0.154",3.90mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$0.158

更新日期:2024-04-01

产品简介:CMOS 可预设置 N 分频计数器

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  • 封装:16-SOIC(0.154",3.90mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$0.158

CD4018BM96 供应商

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  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD4018BM96 中文资料属性参数

  • 标准包装:2,500
  • 类别:集成电路 (IC)
  • 家庭:逻辑 -计数器,除法器
  • 系列:4000B
  • 逻辑类型:除以 N
  • 方向:-
  • 元件数:1
  • 每个元件的位元数:5
  • 复位:异步
  • 计时:同步
  • 计数速率:8.5MHz
  • 触发器类型:正边沿
  • 电源电压:3 V ~ 18 V
  • 工作温度:-55°C ~ 125°C
  • 安装类型:表面贴装
  • 封装/外壳:16-SOIC(0.154",3.90mm 宽)
  • 供应商设备封装:16-SOIC N
  • 包装:带卷 (TR)

产品特性

  • Medium speed operation……10 MHz (typ.) at VDD – VSS = 10 V
  • Fully static operation
  • 100% tested for quiescent current at 20 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications: Fixed and programmable divide-by-10, 9, 8, 7, 6, 5, 4, 3, 2 counters Fixed and programmable counters greater than 10 Programmable decade counters Divide-by-"N" counters/frequency synthesizers Frequency division Counter control/timers
  • Fixed and programmable divide-by-10, 9, 8, 7, 6, 5, 4, 3, 2 counters
  • Fixed and programmable counters greater than 10
  • Programmable decade counters
  • Divide-by-"N" counters/frequency synthesizers
  • Frequency division
  • Counter control/timers

产品概述

CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.The CD4018B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4018BM96 数据手册

数据手册 说明 数量 操作
CD4018BM96

CMOS PRESETTABLE DIVIDE-BY-N COUNTER

12 Pages页,547K 查看
CD4018BM96

Counter IC Divide-by-N 1 Element 5 Bit Positive Edge 16-SOIC

17页,975K 查看

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