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  • 封装:14-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.13635-$0.48

更新日期:2024-04-01

产品简介:2 通道、4 输入、3V 至 18V 与非门

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  • 封装:14-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.13635-$0.48

CD4012BE 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD4012BE 中文资料属性参数

  • 标准包装:25
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 栅极和逆变器
  • 系列:4000B
  • 逻辑类型:与非门
  • 电路数:2
  • 输入数:4
  • 特点:-
  • 电源电压:3 V ~ 18 V
  • 电流 - 静态(最大值):1µA
  • 输出电流高,低:3.4mA,3.4mA
  • 逻辑电平 - 低:1.5 V ~ 4 V
  • 逻辑电平 - 高:3.5 V ~ 11 V
  • 额定电压和最大 CL 时的最大传播延迟:90ns @ 15V,50pF
  • 工作温度:-55°C ~ 125°C
  • 安装类型:通孔
  • 供应商设备封装:14-PDIP
  • 封装/外壳:14-DIP(0.300",7.62mm)
  • 包装:管件
  • 其它名称:296-2032-5

产品特性

  • Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
  • Buffered inputs and outputs
  • Standardized symmetrical output characteristics
  • Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Noise margin (over full package temperature range:     1 V at VDD = 5 V     2 V at VDD = 10 V     2.5 at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

产品概述

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

CD4012BE 数据手册

数据手册 说明 数量 操作
CD4012BE

CMOS NAND GATES

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CD4012BE

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

12 Pages页,526K 查看
CD4012BEE4

CMOS NAND GATES

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