ATMEGA16A-PU

FORCE/DISPLACEMENT/RESISTANCE (FDR) USA: +1.866.928.8181 Europe: +49.0.8031.2460.0 Asia: +86.755.2714.1166 www.lairdtech.com FEATURES ? Fabric-over-Foam gaskets are RoHS compliant ? Halogen-free per IEC-61249-2-21 standard ? UL 94V0 ? Lo w surf ace r esis tivity of < 0.07 Ω / □ pr o vides e x cellen t c onductivity ? Shielding e ff ectiv eness of >100 dB acr oss a wide spectrum of frequencies ? Ex tr emely lo w c ompr ession f or ces allo w f or use of lighter materials ? F abric is highly c onductiv e t o pr o vide g ood EMI shielding and grounding ? Abrasion resistant metallized fabrics sho w virtually no degr ada tion in electric al perf ormance a ft er 1,000,000 cy cles ? Lair d T echnologies’ pr oprie t ar y c oa ting pr e v en ts f abric fr a ying and fing erprin ting ? A v ailable with c onductiv e or non-c onductiv e PS A ? Man y cr oss-section pr ofiles a v ailable such as r ect angle, D , C , P , T , knif e, bell and mo

Features ? High-performance, Low-power AVR ? 8-bit Microcontroller ? Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier ? High Endurance Non-volatile Memory segments – 16K Bytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1K Byte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (1) – Optional Boot Code Section with Independent Lock Bits ? In-System Programming by On-chip Boot Program ? True Read-While-Write Operation – Programming Lock for Software Security ? JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface ? Peripheral Features – Two 8-bit Timer/Counte

Features ? High-performance, Low-power AVR ? 8-bit Microcontroller ? Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier ? High Endurance Non-volatile Memory segments – 16K Bytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1K Byte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (1) – Optional Boot Code Section with Independent Lock Bits ? In-System Programming by On-chip Boot Program ? True Read-While-Write Operation – Programming Lock for Software Security ? JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface ? Peripheral Features – Two 8-bit Timer/Counte

FORCE/DISPLACEMENT/RESISTANCE (FDR) USA: +1.866.928.8181 Europe: +49.0.8031.2460.0 Asia: +86.755.2714.1166 www.lairdtech.com FEATURES ? Fabric-over-Foam gaskets are RoHS compliant ? Halogen-free per IEC-61249-2-21 standard ? UL 94V0 ? Lo w surf ace r esis tivity of < 0.07 Ω / □ pr o vides e x cellen t c onductivity ? Shielding e ff ectiv eness of >100 dB acr oss a wide spectrum of frequencies ? Ex tr emely lo w c ompr ession f or ces allo w f or use of lighter materials ? F abric is highly c onductiv e t o pr o vide g ood EMI shielding and grounding ? Abrasion resistant metallized fabrics sho w virtually no degr ada tion in electric al perf ormance a ft er 1,000,000 cy cles ? Lair d T echnologies’ pr oprie t ar y c oa ting pr e v en ts f abric fr a ying and fing erprin ting ? A v ailable with c onductiv e or non-c onductiv e PS A ? Man y cr oss-section pr ofiles a v ailable such as r ect angle, D , C , P , T , knif e, bell and mo