更新日期:2024-04-01 00:04:00
产品简介:Sitara 处理器: Arm9,LPDDR,DDR2,显示,以太网,PROFIBUS
查看详情AM1810EZWTA3 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
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TI
-
原厂原装
22+ -
3288
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上海市
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-
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一级代理原装
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TI(德州仪器)
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NFBGA-361(16x16)
2022+ -
12000
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上海市
-
-
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原装可开发票
-
TI
-
原厂原装
2318+ -
9200
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合肥
-
-
-
科大讯飞战略投资企业
AM1810EZWTA3 中文资料属性参数
- 现有数量:0现货查看交期
- 价格:90 : ¥197.08778托盘
- 系列:Sitara?
- 包装:托盘
- 产品状态:在售
- 核心处理器:ARM926EJ-S
- 内核数/总线宽度:1 核,32 位
- 速度:375MHz
- 协处理器/DSP:控制系统;CP15
- RAM 控制器:LPDDR,DDR2
- 图形加速:无
- 显示与接口控制器:LCD
- 以太网:10/100Mbps(1)
- SATA:SATA 3Gbps(1)
- USB:USB 1.1 + PHY(1),USB 2.0 + PHY(1)
- 电压 - I/O:1.8V,3.3V
- 工作温度:-40°C ~ 105°C(TJ)
- 安全特性:-
- 安装类型:表面贴装型
- 封装/外壳:361-LFBGA
- 供应商器件封装:361-NFBGA(16x16)
产品特性
- 375-MHz ARM926EJ-S RISC MPU
- ARM926EJ-S Core 32-Bit and 16-Bit (Thumb) Instructions Single-Cycle MAC ARM Jazelle Technology Embedded ICE-RT for Real-Time Debug
- 32-Bit and 16-Bit (Thumb) Instructions
- Single-Cycle MAC
- ARM Jazelle Technology
- Embedded ICE-RT for Real-Time Debug
- ARM9 Memory Architecture 16KB of Instruction Cache 16KB of Data Cache 8KB of RAM (Vector Table) 64KB of ROM
- 16KB of Instruction Cache
- 16KB of Data Cache
- 8KB of RAM (Vector Table)
- 64KB of ROM
- Enhanced Direct Memory Access Controller 3 (EDMA3): 2 Channel Controllers 3 Transfer Controllers 64 Independent DMA Channels 16 Quick DMA Channels Programmable Transfer Burst Size
- 2 Channel Controllers
- 3 Transfer Controllers
- 64 Independent DMA Channels
- 16 Quick DMA Channels
- Programmable Transfer Burst Size
- 128KB of On-Chip Memory
- 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
- Two External Memory Interfaces: EMIFA NOR (8- or 16-Bit-Wide Data) NAND (8- or 16-Bit-Wide Data) 16-Bit SDRAM with 128-MB Address Space DDR2/Mobile DDR Memory Controller with one of the following: 16-Bit DDR2 SDRAM with 256-MB Address Space 16-Bit mDDR SDRAM with 256-MB Address Space
- EMIFA NOR (8- or 16-Bit-Wide Data) NAND (8- or 16-Bit-Wide Data) 16-Bit SDRAM with 128-MB Address Space
- NOR (8- or 16-Bit-Wide Data)
- NAND (8- or 16-Bit-Wide Data)
- 16-Bit SDRAM with 128-MB Address Space
- DDR2/Mobile DDR Memory Controller with one of the following: 16-Bit DDR2 SDRAM with 256-MB Address Space 16-Bit mDDR SDRAM with 256-MB Address Space
- 16-Bit DDR2 SDRAM with 256-MB Address Space
- 16-Bit mDDR SDRAM with 256-MB Address Space
- Three Configurable 16550-Type UART Modules: With Modem Control Signals 16-Byte FIFO 16x or 13x Oversampling Option
- With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
- LCD Controller
- Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
- Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
- Two Master and Slave Inter-Integrated Circuits (I2C Bus)
- One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
- Programmable Real-Time Unit Subsystem (PRUSS) with PROFIBUS Two Independent Programmable Real-Time Unit (PRU) Cores 32-Bit Load-Store RISC Architecture 4KB of Instruction RAM per Core 512 Bytes of Data RAM per Core PRUSS can be Disabled via Software to Save Power Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores. Standard Power-Management Mechanism Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain Dedicated Interrupt Controller Dedicated Switched Central Resource
- Two Independent Programmable Real-Time Unit (PRU) Cores 32-Bit Load-Store RISC Architecture 4KB of Instruction RAM per Core 512 Bytes of Data RAM per Core PRUSS can be Disabled via Software to Save Power Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
- 32-Bit Load-Store RISC Architecture
- 4KB of Instruction RAM per Core
- 512 Bytes of Data RAM per Core
- PRUSS can be Disabled via Software to Save Power
- Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
- Standard Power-Management Mechanism Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain
- Clock Gating
- Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
- USB 1.1 OHCI (Host) with Integrated PHY (USB1)
- USB 2.0 OTG Port with Integrated PHY (USB0) USB 2.0 High- and Full-Speed Client USB 2.0 High-, Full-, and Low-Speed Host End Point 0 (Control) End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
- One Multichannel Audio Serial Port (McASP): Transmit and Receive Clocks Two Clock Zones and 16 Serial Data Pins Supports TDM, I2S, and Similar Formats DIT-Capable FIFO Buffers for Transmit and Receive
- Transmit and Receive Clocks
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
- Two Multichannel Buffered Serial Ports (McBSPs): Transmit and Receive Clocks Supports TDM, I2S, and Similar Formats AC97 Audio Codec Interface Telecom Interfaces (ST-Bus, H100) 128-Channel TDM FIFO Buffers for Transmit and Receive
- Transmit and Receive Clocks
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
- 10/100 Mbps Ethernet MAC (EMAC): IEEE 802.3 Compliant MII Media-Independent Interface RMII Reduced Media-Independent Interface Management Data I/O (MDIO) Module
- IEEE 802.3 Compliant
- MII Media-Independent Interface
- RMII Reduced Media-Independent Interface
- Management Data I/O (MDIO) Module
- Video Port Interface (VPIF): Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
- Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
- Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
- Universal Parallel Port (uPP): High-Speed Parallel Interface to FPGAs and Data Converters Data Width on Both Channels is 8- to 16-Bit Inclusive Single-Data Rate or Dual-Data Rate Transfers Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
- High-Speed Parallel Interface to FPGAs and Data Converters
- Data Width on Both Channels is 8- to 16-Bit Inclusive
- Single-Data Rate or Dual-Data Rate Transfers
- Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
- Serial ATA (SATA) Controller: Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps) Supports all SATA Power Management Features Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries Supports Port Multiplier and Command-Based Switching
- Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps)
- Supports all SATA Power Management Features
- Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
- Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
- Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
- One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
- Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs): Dedicated 16-Bit Time-Base Counter with Period and Frequency Control 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs Dead-Band Generation PWM Chopping by High-Frequency Carrier Trip Zone Input
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
- Three 32-Bit Enhanced Capture (eCAP) Modules: Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs Single-Shot Capture of up to Four Event Time-Stamps
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
- 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
- Extended Temperature
产品概述
The AM1810 ARM Microprocessor
for PROFIBUS is a low-power applications industrial processor based on ARM926EJ-S that is
specifically targeted for PROFIBUS applications.The device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support,
rich user interfaces, and high processing performance life through the maximum flexibility of a
fully integrated mixed processor solution.The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit
instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all
parts of the processor and memory system can operate continuously.The ARM core has a coprocessor 15 (CP15), protection module, and data and program
memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate
16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual
tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data
input/output (MDIO) module; one USB2.0 OTG
interface; one
USB1.1 OHCI interface; two
inter-integrated circuit (I2C Bus) interfaces; one multichannel audio
serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports
(McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects;
four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable
16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with
each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed
with other peripherals; three UART interfaces (each with RTS and
CTS); two enhanced high-resolution pulse width modulator (eHRPWM)
peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3
capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces;
an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and
a higher speed DDR2/Mobile DDR controller.The EMAC provides an efficient interface between the device and a
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or
full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC
supports the MII and RMII interfaces.The SATA controller provides a high-speed interface to mass data
storage devices. The SATA controller supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps).The universal parallel port (uPP) provides a high-speed interface to many types of data
converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8-
to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well
as START, ENABLE, and WAIT signals to provide control for a variety of data converters.A video port interface (VPIF) is included providing a flexible video I/O port.The rich peripheral set provides the ability to control external peripheral devices and
communicate with external processors. For details on each of the peripherals, see the related
sections in this document and the associated peripheral reference guides. The device has a complete set of development tools for the ARM processor. These tools
include C compilers, and scheduling, and a Windows debugger interface for visibility into source code
execution.
AM1810EZWTA3 电路图
AM1810EZWTA3 电路图
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