更新日期:2024-04-01 00:04:00
产品简介:Sitara 处理器: Arm9,SDRAM,以太网
查看详情AM1705DPTPA3 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
HLQFP-176(24x24)
2022+ -
12000
-
上海市
-
-
-
原装可开发票
-
TI
-
原厂原装
2318+ -
9200
-
合肥
-
-
-
科大讯飞战略投资企业
AM1705DPTPA3 中文资料属性参数
- 现有数量:920现货
- 价格:1 : ¥128.39000托盘
- 系列:Sitara?
- 包装:托盘
- 产品状态:在售
- 核心处理器:ARM926EJ-S
- 内核数/总线宽度:1 核,32 位
- 速度:375MHz
- 协处理器/DSP:控制系统;CP15
- RAM 控制器:SDRAM
- 图形加速:无
- 显示与接口控制器:-
- 以太网:10/100Mbps(1)
- SATA:-
- USB:USB 2.0 + PHY(1)
- 电压 - I/O:1.8V,3.3V
- 工作温度:-40°C ~ 105°C(TJ)
- 安全特性:-
- 安装类型:表面贴装型
- 封装/外壳:176-LQFP 裸露焊盘
- 供应商器件封装:176-HLQFP(24x24)
产品特性
- 375- and 456-MHz ARM926EJ-S™ RISC Core 32-Bit and 16-Bit (Thumb®) Instructions Single-Cycle MAC ARM Jazelle® Technology Embedded ICE-RT™ for Real-Time Debug
- 32-Bit and 16-Bit (Thumb®) Instructions
- Single-Cycle MAC
- ARM Jazelle® Technology
- Embedded ICE-RT™ for Real-Time Debug
- ARM9 Memory Architecture 16KB of Instruction Cache 16KB of Data Cache 8KB of RAM (Vector Table) 64KB of ROM
- 16KB of Instruction Cache
- 16KB of Data Cache
- 8KB of RAM (Vector Table)
- 64KB of ROM
- Enhanced Direct Memory Access Controller 3 (EDMA3): 2 Transfer Controllers 32 Independent DMA Channels 8 Quick DMA Channels Programmable Transfer Burst Size
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
- 128KB of RAM Memory
- 3.3-V LVCMOS I/Os (Except for USB Interface)
- Two External Memory Interfaces: EMIFA NOR (8-Bit-Wide Data) NAND (8-Bit-Wide Data) EMIFB 16-Bit SDRAM With 128-MB Address Space
- EMIFA NOR (8-Bit-Wide Data) NAND (8-Bit-Wide Data)
- NOR (8-Bit-Wide Data)
- NAND (8-Bit-Wide Data)
- EMIFB 16-Bit SDRAM With 128-MB Address Space
- 16-Bit SDRAM With 128-MB Address Space
- Three Configurable 16550-Type UART Modules: UART0 With Modem Control Signals 16-Byte FIFO 16x or 13x Oversampling Option Autoflow Control Signals (CTS, RTS) on UART0 Only
- UART0 With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select
- Programmable Real-Time Unit Subsystem (PRUSS) Two Independent Programmable Real-Time Unit (PRU) Cores 32-Bit Load-Store RISC Architecture 4KB of Instruction RAM per Core 512 Bytes of Data RAM per Core PRUSS can be Disabled Through Software to Save Power Standard Power-Management Mechanism Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain Dedicated Interrupt Controller Dedicated Switched Central Resource
- Two Independent Programmable Real-Time Unit (PRU) Cores 32-Bit Load-Store RISC Architecture 4KB of Instruction RAM per Core 512 Bytes of Data RAM per Core PRUSS can be Disabled Through Software to Save Power
- 32-Bit Load-Store RISC Architecture
- 4KB of Instruction RAM per Core
- 512 Bytes of Data RAM per Core
- PRUSS can be Disabled Through Software to Save Power
- Standard Power-Management Mechanism Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain
- Clock Gating
- Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
- Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO)
- Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
- USB 2.0 OTG Port With Integrated PHY (USB0) USB 2.0 Full-Speed Client USB 2.0 Full- and Low-Speed Host End Point 0 (Control) End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
- USB 2.0 Full-Speed Client
- USB 2.0 Full- and Low-Speed Host
- End Point 0 (Control)
- End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
- Two Multichannel Audio Serial Ports (McASPs): Six Clock Zones and 28 Serial Data Pins Supports TDM, I2S, and Similar Formats FIFO Buffers for Transmit and Receive
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
- 10/100 Mbps Ethernet MAC (EMAC): IEEE 802.3 Compliant (3.3-V I/O Only) RMII Media-Independent Interface Management Data I/O (MDIO) Module
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
- One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
- One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
- Three Enhanced Pulse Width Modulators (eHRPWMs): Dedicated 16-Bit Time-Base Counter With Period and Frequency Control 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs Dead-Band Generation PWM Chopping by High-Frequency Carrier Trip Zone Input
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
- Three 32-Bit Enhanced Capture (eCAP) Modules: Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs Single-Shot Capture of up to Four Event Timestamps
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Timestamps
- Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
- 176-Pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
- Commercial, Industrial, or Extended Temperature
产品概述
The AM1705 is a
low-power ARM microprocessor based on an ARM926EJ-S.The device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user
interfaces, and high processor performance through the maximum flexibility of a fully integrated,
mixed processor solution.The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit
instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of
the processor and memory system can operate continuously.The ARM core has a coprocessor 15 (CP15), protection module, and data and program
memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of
instruction and 16-KB data caches. Both memory blocks are 4-way associative with virtual index
virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data
input/output (MDIO) module; two I2C Bus interfaces; three multichannel
audio serial ports (McASPs) with serializers and FIFO
buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog);
up to 8 banks of 16
pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes,
multiplexed with other peripherals; three UART interfaces (one with both RTS
and CTS); three enhanced high-resolution pulse width modulator (eHRPWM)
peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3
capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature
encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory
interface (EMIFB) for SDRAM.The Ethernet Media Access Controller (EMAC) provides an efficient interface between the
device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in
either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY
configuration. The I2C, SPI,
and USB2.0 ports allow the device to easily control
peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices
and communicate with external processors. For details on each peripheral, see the related sections
later in this document and the associated peripheral reference guides. The device has a complete set of development tools for the ARM processor. These tools
include C compilers and a Windows® debugger interface for visibility into source code
execution.
AM1705DPTPA3 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
ARM926EJ-S Microprocessor IC Sitara? 1 Core, 32-Bit 375MHz 176-HLQFP (24x24) |
165页,1.29M | 查看 |
AM1705DPTPA3 电路图

AM1705DPTPA3 电路图
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