您好,欢迎来到知芯网
  • 封装:64-VFQFN 裸露焊盘
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$103.0472-$97.439

更新日期:2024-04-01 00:04:00

产品简介:四通道、12 位、125MSPS 模数转换器 (ADC)

查看详情
  • 封装:64-VFQFN 裸露焊盘
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$103.0472-$97.439

ADS6425IRGCT 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

ADS6425IRGCT 中文资料属性参数

  • 产品培训模块:Data Converter Basics
  • 视频文件:ADS6425 Quad 12-bit 125MSPS ADC
  • 标准包装:1
  • 类别:集成电路 (IC)
  • 家庭:数据采集 - 模数转换器
  • 系列:-
  • 位数:12
  • 采样率(每秒):125M
  • 数据接口:串行,并联
  • 转换器数目:4
  • 功率耗散(最大):-
  • 电压电源:模拟和数字
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:64-VFQFN 裸露焊盘
  • 供应商设备封装:64-VQFN 裸露焊盘(9x9)
  • 包装:®
  • 输入数目和类型:4 个差分,单极
  • 配用:296-30692-ND - EVAL MODULE FOR ADS6425
  • 其它名称:296-21696-6

产品特性

  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 1.65-W Total Power
  • Simultaneous Sample and Hold
  • 70.3 dBFS SNR at Fin = 50 MHz
  • 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
  • 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp Differential
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64 QFN Package (9 mm × 9 mm)
  • Pin Compatible 14-Bit Family (ADS644X - SLAS532)
  • APPLICATIONS Base-Station IF Receivers Diversity Receivers Medical Imaging Test Equipment
  • Base-Station IF Receivers
  • Diversity Receivers
  • Medical Imaging
  • Test Equipment

产品概述

The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes a 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB. The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling frequencies.An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes, and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.The ADS6425 has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (-40°C to 85°C).

ADS6425IRGCT 数据手册

数据手册 说明 数量 操作
ADS6425IRGCT

12 Bit Analog to Digital Converter 4 Input 4 Pipelined 64-VQFN (9x9)

59页,2.13M 查看

ADS6425IRGCT 电路图

ADS6425IRGCT 电路图

ADS6425IRGCT 电路图

IC 索引: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9