- 封装:48-VFQFN 裸露焊盘
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$43.05
更新日期:2024-04-01 00:04:00
产品简介:12 位、170MSPS 模数转换器 (ADC)
查看详情- 封装:48-VFQFN 裸露焊盘
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$43.05
ADS5525IRGZR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
VQFN-48(7x7)
2022+ -
12000
-
上海市
-
-
-
原装可开发票
ADS5525IRGZR 中文资料属性参数
- 产品培训模块:Data Converter Basics
- 标准包装:2,500
- 类别:集成电路 (IC)
- 家庭:数据采集 - 模数转换器
- 系列:-
- 位数:12
- 采样率(每秒):170M
- 数据接口:串行,并联
- 转换器数目:1
- 功率耗散(最大):1.28W
- 电压电源:模拟和数字
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:48-VFQFN 裸露焊盘
- 供应商设备封装:48-VQFN 裸露焊盘(7x7)
- 包装:带卷 (TR)
- 输入数目和类型:1 个差分,单极
产品特性
- Maximum Sample Rate: 170 MSPS
- 12-Bit Resolution
- No Missing Codes
- Total Power Dissipation 1.1 W
- Internal Sample and Hold
- 70.5-dBFS SNR at 70-MHz IF
- 84-dBc SFDR at 70-MHz IF
- 11 bits ENOB Minimum at 70-MHz IF
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
- Reduced Power Modes at Lower Sample Rates
- Supports input clock amplitude down to 400 mVPP
- Clock Duty Cycle Stabilizer
- No External Reference Decoupling Required
- Internal and External Reference Support
- Programmable Output Clock position to ease data capture
- 3.3-V Analog and Digital Supply
- 48-QFN Package (7 mm × 7 mm)
- APPLICATIONSWireless Communications InfrastructureSoftware Defined RadioPower Amplifier Linearization802.16d/eTest and Measurement InstrumentationHigh Definition VideoMedical ImagingRadar Systems
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
产品概述
ADS5525 is a high performance 12-bit, 170-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5525 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode. The device is specified over the industrial temperature range (-40°C to 85°C).
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