更新日期:2024-04-01 00:04:00
产品简介:7 位、双路 1.5GSPS 或单路 3.0GSPS 模数转换器 (ADC)
查看详情ADC07D1520CIYB/NOPB 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
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TI
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原厂原装
22+ -
3288
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上海市
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-
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一级代理原装
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TI
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HLQFP
21+ -
128
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上海市
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原装现货,品质为先!请来电垂询!
ADC07D1520CIYB/NOPB 中文资料属性参数
- 现有数量:120现货9,960Factory
- 价格:1 : ¥1,558.34000托盘
- 系列:-
- 包装:托盘
- 产品状态:在售
- 位数:7
- 采样率(每秒):3G
- 输入数:2
- 输入类型:差分
- 数据接口:LVDS - 并联
- 配置:MUX-S/H-ADC
- 比率 - S/H:ADC:1:1
- A/D 转换器数:2
- 架构:折叠内插
- 参考类型:内部
- 电压 - 供电,模拟:1.8V ~ 2V
- 电压 - 供电,数字:1.8V ~ 2V
- 特性:同步采样
- 工作温度:-40°C ~ 85°C
- 封装/外壳:128-LQFP 裸露焊盘
- 供应商器件封装:128-HLQFP(20x20)
- 安装类型:表面贴装型
产品特性
- Single +1.9V ±0.1V Operation
- Interleave Mode for 2x Sample Rate
- Multiple ADC Synchronization Capability
- Adjustment of Input Full-Scale Range, Clock Phase, and Offset
- Choice of SDR or DDR Output Clocking
- 1:1 or 1:2 Selectable Output Demux
- Second DCLK Output
- Duty Cycle Corrected Sample Clock
- Test pattern
产品概述
The ADC07D1520 is a dual, low power, high performance CMOS analog-to-digital converter. The ADC07D1520 digitizes signals to 7 bits of resolution at sample rates up to 1.5 GSPS. Its features include a test pattern output for system debug, a clock phase adjust, and selectable output demultiplexer modes. This device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 6.8 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10 -18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ is at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a leaded or lead-free, 128-pin, thermally enhanced, exposed pad LQFP and operates over the Industrial (40°C ≤ TA ≤ +85°C) temperature range.
ADC07D1520CIYB/NOPB 电路图
ADC07D1520CIYB/NOPB 电路图
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