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  • 封装:7-LSSOP(0.11"?,2.80mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$0.186

更新日期:2024-04-01

产品简介:具有施密特触发输入的 2 通道、2 输入、1.65V 至 5.5V 与非门

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  • 封装:7-LSSOP(0.11"?,2.80mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$0.186

74LVC2G132DCTRG4 供应商

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74LVC2G132DCTRG4 中文资料属性参数

  • 标准包装:3,000
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 栅极和逆变器
  • 系列:74LVC
  • 逻辑类型:与非门
  • 电路数:2
  • 输入数:2
  • 特点:施密特触发器
  • 电源电压:1.65 V ~ 5.5 V
  • 电流 - 静态(最大值):10µA
  • 输出电流高,低:32mA,32mA
  • 逻辑电平 - 低:0.39 V ~ 1.87 V
  • 逻辑电平 - 高:1.16 V ~ 3.33 V
  • 额定电压和最大 CL 时的最大传播延迟:5ns @ 5V,50pF
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 供应商设备封装:SM8
  • 封装/外壳:7-LSSOP(0.11"?,2.80mm 宽)
  • 包装:带卷 (TR)

产品特性

  • Available in Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
  • Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

产品概述

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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