HEF4013BT

Dual D-type flip-flop

1. General description The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended V DD power supply range of 3 V to 15 V referenced to V SS (usually ground). Unused inputs must be connected to V DD , V SS , or another input. 2. Features and benefits ? Tolerant of slow clock rise and fall times ? Fully static operation ? 5 V, 10 V, and 15 V parametric ratings ? Standardized symmetrical output characteristics ? Specified from ?40 ?C to +125 ?C ? Complies with JEDEC standard JESD 13-B 3. Applications

DATA SHEET Product speci?cation File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4013B flip-flops Dual D-type flip-flop For a complete data sheet, please also download: ? The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC ? The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

DATA SHEET Product speci?cation File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4013B flip-flops Dual D-type flip-flop For a complete data sheet, please also download: ? The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC ? The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

1. General description The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended V DD power supply range of 3 V to 15 V referenced to V SS (usually ground). Unused inputs must be connected to V DD , V SS , or another input. 2. Features and benefits ? Tolerant of slow clock rise and fall times ? Fully static operation ? 5 V, 10 V, and 15 V parametric ratings ? Standardized symmetrical output characteristics ? Specified from ?40 ?C to +125 ?C ? Complies with JEDEC standard JESD 13-B 3. Applications

Dual D-type flip-flop